1. Technical Field
The present invention relates to a PLL (Phase Locked Loop) circuit and a method of controlling the same, and in particular, to a PLL circuit that stably performs a phase locking operation of a clock and a method of controlling the same.
2. Related Art
With the advancement of a higher-speed semiconductor memory apparatus, the frequency of an external clock increases, and accordingly the frequency of an internal clock also increases. With the increase in frequency of the internal clock, in the known semiconductor memory apparatus that uses a DLL (Delay Locked Loop) circuit, an operation to input/output data in synchronization with a clock becomes unstable. In particular, in a high-speed semiconductor memory apparatus, such as a graphic memory or the like, since a timing margin between a data strobe signal generated by the clock and data is decreased, reliability of a data input operation is deteriorated.
In a current semiconductor memory apparatus, a method that uses a PLL circuit in order to improve reliability of the data input operation has been introduced. This semiconductor memory apparatus compares the timing of the clock and input data with each other using the PLL circuit to measure a phase difference. Then, the phase of the data is controlled with respect to the clock, such that the data is in phase with the clock. Therefore, reliability of the data input operation is improved.
A general PLL circuit includes a low pass filter that pumps a voltage by the pull-up control signal and the pull-down control signal, and removes noise from the pumped voltage.
As shown in FIG. 1, the low pass filter includes a charge pump and a filter unit 6 in general. The charge pump includes pull-up pump unit 2 and a pull-down pump unit 4.
The pull-up pump unit 2 has a first voltage pump 3 and a PMOS transistor PMOS. The first voltage pump 3 generates a first pumping voltage Vpmp1 from an external power supply VDD. The PMOS transistor PMOS supplies the first pumping voltage Vpmp1 to a first node N1 in response to the pull-up control signal plup.
The pull-down pump unit 4 has an NMOS transistor and a second voltage pump 5. The NMOS transistor NMOS transmits a voltage of the first node N1 to the second voltage pump 5 in response to the pull-down control signal pldn. The second voltage pump 5 pumps the voltage of the first node N1 transmitted from the NMOS transistor NMOS to a second pumping voltage Vpmp2, and supplies the pumped voltage to the ground terminal VSS. That is, general charge pump receives the pull-up control signal plup and the pull-down control signal pldn.
The filter unit 6 removes a noise component of a signal applied to the first node N1 and outputs the signal with no noise component as a control voltage Vctrl. The filter unit 6 may include one capacitor and one resistor.
Generally, in the PLL circuit, if the input clock and the feedback clock are in phase, the pull-up control signal plup and the pull-down control signal pldn input to the low pass filter are all enabled. At this time, the first node N1 has a signal having a constant level, and the phase of the clock is fixed corresponding to the signal generated at the first node N1. However, the signal formed at the first node N1, which is a connection node of the pull-up pump unit 2 and the pull-down pump unit 4 constituting the charge pump of the low pass filter, does not have a constant level. This is caused by a difference in operability between the first voltage pump 3 and the second voltage pump 5, a difference in resistance between the PMOS transistor PMOS and the NMOS transistor NMOS, and a difference in characteristic between the PMOS transistor and the NMOS transistor due to PVT (Process, Voltage, and Temperature) factors.
As such, if the connection node between the pull-up pump unit 2 and the pull-down pump unit 4 of the low pass filter does not keep the signal having the constant level, the control voltage Vctrl may not fall within a prescribed swing range, and as a result, a voltage ripple phenomenon that the final output clock does not fall within a prescribed frequency band may occur. This voltage ripple phenomenon causes an error in the phase locking operation of the clock.
Further, the voltage ripple phenomenon may grow heavier due to a difference in current between the pull-up pump unit 2 and the pull-down pump unit 4 constituting the charge pump of the low pass filter, a difference in electric charge injection amount, a difference in electric charge division amount, and p/n mismatching of the components constituting the pump units 2 and 4.